SBIR/STTR Research Award

Fault Tolerant, Radiation hard DSP

Award identifier 67258511da4855fb906b943807eb49e5af31267e77c2deed9f15341f42c9ab80Awarding agency National Aeronautics and Space Administration

Award amount

$70,000

Program and phase

SBIR · Phase I

Award year

2005

Explore This Research Award in CaptureIQ

Research the technology, evaluate the recipient and agency, identify related opportunities, and explore potential follow-on work with CaptureIQ.

Award details

Awarding agency
National Aeronautics and Space Administration
Branch
Not reported
Recipient company
Space Micro Inc.
Proposal award date
2005-01-19
Contract end date
2005-07-25
UEI
ED9EEK4ZRZG4
Solicitation number
Not reported
Topic code
X7.01

Research abstract

Commercial digital signal processors (DSP) are problematic for satellite computers due to damaging space radiation effects, particularly single event upsets (SEU) and functional interrupts (SEFI). Space Micro has developed innovations for mitigating SEU and SEFI errors, enabling the use of very high-speed commercial DSPs with improved SEU tolerances (>1E-4 unrecoverable errors/day). Time-Triple Modular Redundancy (TTMR) is a method of applying traditional triple modular redundancy on a single processor, exploiting the VLIW class of parallel processors. SEFI is solved by a Hardened Core circuit, external to the microprocessor, which monitors the "health" of the processor, and when SEFI occurs, forces the processor to return to performance through a series of escalating events (interrupts, reset, etc). In Phase I we apply these technologies to COTS DSPs and also will extend the TTMR and Hardened Core architecture to reconfigurable FPGA arrays, with dramatically improved SEU/SEFI rates for Xilinx FPGAs. In Phase II we will provide SEU & SEFI hardened DSP plus FPGA product, with performance of 8,000 MIPS fixed point and 1.8 GFLOPS floating point (derated approximately 50% for improved SEU performance) while consuming less than 2 watts power, combined with an array of Xilinx reconfigurable FPGAs, providing approximately 7500 MFLOPS per FPGA.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

150 SBIR/STTR records share this UEI (2002–2023). Reported award amounts total $58,449,422. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Homeland Security

Agency intelligence

National Aeronautics and Space Administration

Back to SBIR/STTR Research Awards

Don't take our word for it. Ask AI about RFPCapture.

See what leading AI assistants have to say about RFPCapture and CaptureIQ.

Gemini opens without a prefilled question. The question is copied to your clipboard when the button works. You can also copy it here:

What is RFPCapture.com and its CaptureIQ platform from Smart Logic AI? How does it help federal contractors discover opportunities, evaluate bid/no-bid decisions, research government contracts, and prepare proposals? How does it compare with other federal capture platforms? Use independent sources where available.