Radiation Hardness by Design and Integration Production of 8-16 Mega-bit SRAM

This program will demonstrate at scale, that radiation hardness by design (HBD)of 8-16 Mega-bit SRAM of state-of-the-art (0.25-0.13µm) commercially fabricated CMOS materials with prompt dose hardness targeted to exceed 1E11 Rad(Si)/sec. The Phase I effort showed that MDA strategic needs could be advantageously meet in a commercial fabrication line, thus minimizing cost and leveraging commercial product yield. In Phase I, we demonstrated greater than 1.3 E 10 Rad-Si/sec prompt dose (the limit of the source radiation) without failure. Further, simple SPICE modeling of the data show that the commercial process has the potential to maintain resistance to prompt dose effects when scaled from test chip to 8-16 Mega-bit SRAM strategically hardened products. The successful completion of the Phase I effort supports that a high density "strategic" Rad Hard SRAM can be manufactured on a commercial fabrication line. Our Phase II will build upon our Phase I results to design and fabricate a strategically dose-rate hardened SRAM.