Technology for Affordable Validation and Verification (V&V) Software Design Processes and Safe Flight-Critical Software
Award amount
$100,000Program and phase
SBIR · Phase IAward year
2004Award details
- Awarding agency
- Department of Defense
- Branch
- Air Force
- Recipient company
- EDAPTIVE COMPUTING INC
- Proposal award date
- 2004-05-19
- Contract end date
- 2005-03-19
- UEI
- ULSZZUD8P7W7
- Solicitation number
- 2004.1
- Topic code
- AF04-246
Research abstract
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- ARMED Phase II
- Synthesizable Register Transfer Logic (RTL) Assertions
- SEAMLESS: Secured and Assured Machine Learning Systems
- Automatic FPGA and IC Run-time Monitor (AFIRM)
- ARMED: Automatic Requirements Mapping to Architecture Diagrams
Awards with the same topic code
Verified by an exact topic code match. This is not a text-similarity match.
- Run-time Verification and Validation for Safety-Critical Flight Control Systems
- Technology for Affordable Validation and Verification (V&V) Software Design Processes and Safe Flight-Critical Software
- Affordable Run-Time Verification & Validation of Flight Critical Software
- Technology for Affordable Validation and Verification (V&V) Software Design Processes and Safe Flight-Critical Software
- Run-time Verification and Validation for Safety-Critical Flight Control Systems
Research funding history
92 SBIR/STTR records share this UEI (1999–2023). Reported award amounts total $45,452,067. Reported amounts are not federal obligations.
Phases: Phase I, Phase II, Phase II – Direct to Phase II
Agencies: Department of Defense, National Aeronautics and Space Administration, National Science Foundation