Asynchronous Architectures for Large-Integer Processors with Applications to Security

The proposed research is concerned with the design and implementation of asynchronous architectures for a large integer processor (LIP) able to perform arithmetic operations, in particular multiplications, on integers of a size that current synchronous architectures cannot handle efficiently (say, 5000~bits). The main application is security, in particular public-key and mixed private-key/public-key cryptography. A LIP will be a large processor array used as a coprocessor. A LIP-based system will be able to perform public-key encryption at a fraction of the runtime and/or energy consumption of current hardware platforms due to the use of asynchronous techniques. The LIP will be software-reconfigurable for different cryptographic protocols and different phases in each protocol. We will include finer-grain reconfigurable hardware (such as that found in FPGAs) in order to accelerate certain cryptographic protocols (especially those including private-key cryptography). The architecture will be evaluated for its radiation-hardness and several designs may be presented (non-hardened, radhard-by-design; different levels of reconfigurability) in order to match user requirements. Phase~I will implement unclassified algorithms. For Phase II, we are considering moving to classified algorithms in collaboration with Mykotronx. The LIP architecture will leverage work done at Caltech on clustered architecture for asynchronous FPGAs, and work done at Situs Logic on radhard-by-design asynchronous VLSI and CAD tools for asynchronous VLSI.