CAD Tools for Clockless Circuit and System Design and Test

Asynchronous circuit design has the potential to offer orders of magnitude improvement in speed, power dissipation and EMI over synchronous circuit design. It is especially appealing to military electronics due to its extremely low EMI performance and its suitability as an enabling technology for heterogeneous system integration with high reliability and affordability. However, its real silicon success has been extremely limited due to lack of supporting design and test tools. In this SBIR project, we propose to develop three innovative CAD tools (CASTER, Arsyn-D and AFIST) to address the missing yet critical links for a complete clockless circuit design and test flow. CASTER (CMOS Asynchronous System Timing, Energy and Radiation) is the first CAD tool for silicon-accurate analysis and optimization of timing, power and EMI of asynchronous circuits. It provides a fast engine for clockless circuit optimization, as well as a standard tool and metrics for the final sign off of clockless design, and evaluation of different design styles. Arsyn-D is a million-transistor scale optimization tool for clockless circuits that incorporates automatic asynchronous topology selection to address military requirements. AFIST is the first realistic fault modeling based test generation and diagnosis tool for asynchronous circuits, based on innovative behavioral fault modeling technologies. We propose to team up with Boeing Solid State Electronics to demonstrate the proposed tools on military electronics design, in particular, to DARPA/CLASS program benchmarks.