Testing Methodology/Tools for Asynchronous Circuits

Theseus Logic, in partnership with FTL Systems, intends to integrate test and verification into their commercial design automation tool that will aid the designer by providing the means to automatically insert testability into clockless circuits. Success in this endeavor will eliminate one of the remaining obstacles that hinders widespread adoption of asynchronous design approaches for DoD and commercial applications. This proposal will involve the enhancement and integration of algorithms developed in Phase I as well as expanding the scope of the sub-circuits evaluated. It will also develop the framework necessary for performance analysis of NULL Convention Logic circuits. At the end of Phase II, the EDA tool commercially available from FTL Systems will have the following new features for support of clockless circuits: o The ability to seamlessly insert scan into a clockless design. o The ability to automatically generate a set of test vectors for the circuit. o The ability to measure the fault coverage from a set of test vectors. o The ability to support test vector generation by the TetraMAX ATPG tool.