THE DEVELOPMENT OF AN INTELLIGENT VAXBI FASTBUS INTERFACE

AN INTELLIGENT LIST-PROCESSING INTERFACE BETWEEN THE VAXBI AND FASTBUS WILL BE DEVELOPED. THE VAXBI IS THE 13.3 MEGABYTE/SEC BACKPLANE INTERCONNECT FEATURED IN VAX 8200, 8300, 8800, AND OTHER FUTURE VAX COMPUTER SYSTEMS. THE INTENT IS TO PROVIDE A HIGH BANDWIDTH GATEWAY BETWEEN A VARIETY OF VAX CONFIGURATIONS, INCLUDING SINGLE PROCESSORS, MULTIPROCESSORS, AND CLUSTERED PROCESSORS, AND THE FASTBUS. THE HARDWARE CONSISTS OF A FASTBUS INTERFACE, A VAXBI INTERFACE, AND ONE OR MORE PROCESSORS PROVIDING THE INTERFACE INTELLIGENCE. THE FASTBUS INTERFACE USES EITHER ONE OF A PAIR OF PLUG-COMPATIBLE FASTBUS CARDS BEING DEVELOPED. A HIGH BANDWIDTH CARD IMPLEMENTED IN ECL 2500 GATE MACROCELL ARRAYS HAS BEEN DEVELOPED AS WELL AS A COMPATIBLE INTERFACE IN TTL PAL AND IFL TECHNOLOGY. THE VAXBI INTERFACE WILL BE EITHER A DRB-32 VAXBI MODULE WITH MODIFIED MICROCODE, A FUTURE VAXBI I/O PROCESSOR INTERFACE PROVIDED BY DIGITAL EQUIPMENT CORPORATION, OR A CUSTOM VAXBI INTERFACE TO BE DESIGNED IN PHASE II. INTELLIGENCE WILL BE PROVIDED EITHER BY A MICROPROCESSOR IN THE FUTURE DEC I/O PROCESSOR OR BY AN OUTBOARD 16-BIT MICROPROCESSOR. BESIDES THE USUAL SUPPORT FOR A FASTBUS INTERFACE, SOFTWARE DEVELOPMENT WILL FOCUS ON THREE MAJOR AREAS: (1) THE MAPPING OF VIRTUAL MEMORY, WHICH MUST BE PROVIDED BY INTERFACES ON A PHYSICALLY ADDRESSED I/O BUS SUCH AS THE VAXBI; (2) METHODS OF SHARING A SINGLE FASTBUS INTERFACE AMONG MULTIPLE PROCESSORS ON A SINGLE VAXBI; AND (3) THE POSSIBILITY OF PROVIDING TRANSPARENT ACCESS TO A SINGLE FASTBUS INTERFACE TO ALL MEMBERS OF A VAX CLUSTER.