SBIR/STTR Research Award

Multi-processor Embedded Front-End Electronics Platform with Multi-Function Network for Pulsed Accelerator Control Systems

Award identifier 456c9c32c48e5be3cb8de3e41944d6f14428858a72df0ed663db4e921521574fAwarding agency Department of Energy

Award amount

$99,996

Program and phase

SBIR · Phase I

Award year

2005

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Award details

Awarding agency
Department of Energy
Branch
Not reported
Recipient company
Nycb Real-time Computing, Inc.
Proposal award date
Not reported
Contract end date
Not reported
UEI
JGM2XZRM8FN1
Solicitation number
DE-FG02-06ER06-09
Topic code
36

Research abstract

78911S Electronics for pulsed front-end devices at pulsed particle accelerators are typically accessed through up to 4 networks, which carry timing information, pulse-to-pulse sequencing, real-time streaming data, and configuration information, respectively. Although modern commercial networks offer a rich variety of features, they are not well optimized to the needs of pulsed accelerators for clocking, pulse-by-pulse control, or reliable real-time data acquisition with sub-millisecond timeouts in an electrically noisy environment. In this project, circuit switching will be used to provide preferential delivery of real-time data streams, with error correction adding noise immunity. The accelerator clock frequency will be carried by synchronizing the data link byte clock to the accelerator clock. Clock phase and fiducial timing data will be sent by custom extensions to the circuit switching protocols. Separate embedded power PC processors coupled via shared memory within a single field programmable gate array (FPGA) will be employed for real-time and non-real-time functions. Phase I will extend a previously developed approach for circuit switching both real-time and non-real-time data onto a single network physical link to carry accelerator clock and fiducial timing data. An additional technology for coupling multiple power PC processors, embedded within a single FPGA via shared memory, also will be developed. Both technologies will be combined with a dual-access PCI (Peripheral Component Interconnect) master, in an FPGA design intended for use, on a demonstration hardware platform packaged as a PCI mezzanine card. Commercial Applications and Other Benefits as described by the awardee: The technology should find application in computer network interface cards, network fabric switching points, and embedded device controllers for accelerator devices. The use of such techniques should lead to more reliable accelerators.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

15 SBIR/STTR records share this UEI (1983–2008). Reported award amounts total $3,511,010. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Energy, Department of Health and Human Services

Agency intelligence

Department of Energy

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