3D Silicon MIMD/SIMD Massively Parallel Processor

Irvine Sensors proposes to use its 3D silicon chip stacking technology to provide the increase in packaging density required to support second-generation massively parallel computers. Using the third dimension to stack processor devices, promises to reduce substrate cost in direct relation to the number of processors stacked meeting the ten fold or more improvement in substrate costs by reducing the required substrate area. In addition, power and performance figures of merit will be improved as well. Reduced capacitive loading, caused by the asbsence of packages and by 3D silicon's extremely short interconnection wiring lines will lead to even better performance and lower power dissipation that previsouly achieved in other hybrid-WSI technologies. Typical interchip bussing distances for 3D silicon are on the order of tens of mils (0.010 inches), while those associated with other technologies are on the order of hundreds of mils. Also, Irvine Sensors' interconnect technology is pure resistive versus standard wire bonds which contain a good deal of inductance. This means less noise, and less current to charge and discharge signal nodes increasing performance and minimizing power.