A FORMAT FREE GIGABIT/SECOND OPTICAL FIBER DATA ACQUISTION INTERFACE

A DATA ACQUISITION INTERFACE IS BEING DEVELOPED FOR ELEMENTARY PARTICLE PHYSICS DATA TRANSPORTED ON OPTICAL FIBER AT BANDWIDTHS UP TO ONE GIGABIT PER SECOND. THE INTERFACE IS INTENDED AS A DEVELOPMENT TOOL DURING THE ENGINEERING OF PROTOTYPE DATA ACQUISITION ELECTRONICS FOR USE IN FUTURE LARGE HIGH BANDWIDTH EXPERIMENTS SUCH AS THOSE AT THE SUPERCONDUCTING SUPER COLLIDER (SSC). NO PARTICULAR FORMAT OR NETWORK PROTOCOL NEEDS TO BE IMPOSED ON THE INCOMING DATA, ALTHOUGH THE INTERFACE CAN BE CONFIGURED TO SUPPORT USER DEFINED FORMATS. THE PLANNED INTERFACE IS MODULAR AND EXPANDABLE. IT IS CAPABLE OF (1) RECEIVING DATA BLOCKS FROM MORE THAN ONE FIBER AT A TIME, AND (2) FURNISHING THE INCOMING DATA TO CONSUMERS AT MORE THAN ONE DESTINATION. POSSIBLE DESTINATIONS INCLUDE THE DIRECTLY CONNECTED INPUT/OUTPUT (I/O) INTERCONNECTS OF WORKSTATIONS OR PERSONAL COMPUTERS AS WELL AS STANDARD NETWORKS. THE INITIAL I/O BUS CONNECTION WILL BE VIA SMALL COMPUTER SYSTEM INTERFACE; AND THE INITIAL NETWORK CONNECTION FOR DATA READOUT WILL BE THE ETHERNET. THE PRIMARY INTENT IS TO FREE THE DESIGNER OF FRONT-END ELECTRONICS WITH FIBER READOUT FROM THE NEED TO ACQUIRE EXPERTISE IN EITHER NETWORK PROTOCOLS OR THE DETAILS OF I/O INTERFACING TO WORKSTATIONS, PERSONAL COMPUTERS, OR OTHER USER-FRIENDLY COMPUTING PLATFORMS DURING THE TURN-ON, DEBUGGING, AND EARLY COSMIC-RAY OR TEST BEAM EVALUATION PHASES OF ELECTRONICS DEVELOPMENT. SYSTEM ARCHITECTURE FEATURES VME FOR CONTROL, CONFIGURATION, TESTING, AND LOW BANDWIDTH ACCESS TO DATA BLOCKS, AS WELL AS A DEDICATED 128 MEGABYTE/SECOND BLOCK TRANSPORT PATH, WHICH WOULD ENABLE A DATA BLOCK RECEIVED AT AN INPUT MODULE TO BE DISTRIBUTED TO ONE OR MORE OUTPUT MODULES WITH A MINIMUM AMOUNT OF PROTOCOL OVERHEAD. THE PHASE I EFFORT FOCUSES ON DETERMINING THE RANGE OF PARAMETERS OVER WHICH THE INTERFACE IS CONFIGURABLE, ESTABLISHING THE COMPLETE HARDWARE AND SOFTWARE ARCHITECTURE, AND DESIGNING THE BASE LEVEL HARDWARE. THE ARCHITECTURE AND ENGINEERING DESIGNS DEVELOPED IN PHASE I WILL THEN FORM THE BASIS OF A COMPLETE WORKING PROTOTYPE UNIT TO BE IMPLEMENTED IN PHASE II.