A SUPERCONDUCTING SINGLE-CHIP MULTI-CHANNEL TIMING ANALYZER FOR PARTICLE DETECTORS

THIS PROJECT STUDIES THE BASIC ELEMENTS REQUIRED FOR A MULTI-CHANNEL TIME-OF-FLIGHT (TOF) ANALYZER. THE TOF ANALYZER USES A SUPERCONDUCTING ACQUISITION SHIFT REGISTER (ASR) AND NOVEL FRONT-END DETECTOR BASED ON RECENTLY REPORTED RAPID SINGLE FLUX QUANTUM LOGIC. THIS SYSTEM IS CAPABLE OF CLOCKING FREQUENCIES TO 100 GHZ. THE PLANNED ASR CIRCUIT REQUIRES DATA AT 50 SAMPLES/SECOND (S/S) FOR A 20 PICOSECOND (PS) TIME RESOLUTION. THE DATA ARE BEING WRITTEN OUT TO CONVENTIONAL ELECTRONICS AT MHZ FREQUENCIES. THE ULTIMATE GOAL IS A FULLY SYNCHRONIZED 20 PS RESOLUTION, 10,000 CHANNEL SYSTEM WITH A TOTAL POWER DISSIPATION OF 25 W. THIS SYSTEM WILL REQUIRE 1,250 CHIPS, EACH WITH AN AREA OF 1 CM(2). ADDITIONALLY, THE COST PER CHANNEL HAS THE POTENTIAL OF BEING VERY LOW-LESS THAN $12 PER CHANNEL. THE ASR CIRCUIT IS BASED ON SUPERCONDUCTING MICROELECTRONICS THAT CAN RUN AT VERY HIGH SPEEDS WITH EXTREMELY LOW POWER DISSIPATION. FURTHERMORE, THE ACTIVE DEVICES HAVE VERY LOW SENSITIVITY TO RADIATION. PHASE I SHOULD DEMONSTRATE THE PRINCIPLES OF OPERATING AN ASR. A NIOBIUM SUPERCONDUCTING INTEGRATED CIRCUIT (THE ASR) IS BEING FABRICATED AND TESTED. SPECIFICALLY, HIGH SPEED SHIFT REGISTERS (50 GHZ GOAL) ARE BEING DEMONSTRATED WITH APPROPRIATE TRIGGER AND TIMING CIRCUITS TO READ DATA IN AT HIGH SPEEDS AND WRITE DATA OUT AT LOW SPEEDS. IN ADDITION, A PULSE DIFFERENTIATOR CIRCUIT IS BEING STUDIED AS THE NOVEL FRONT END THAT HAS A COMPATIBLE SPEED WITH THE SHIFT REGISTER. THE ENVISIONED DETECTOR WILL BE ABLE TO SENSE EXACT TIME LOCATION OF THE PULSE PEAK. THE DETECTOR WILL ALSO DETERMINE THE PULSE DURATION, WHICH WILL ALLOW AN ESTIMATE OF THE PULSE HEIGHT.