ARRAY COMMUNICATIONS COPROCESSOR

AN ARRAY COMMUNICATIONS COPROCESSOR (ACC) ARCHITECTURE HAS BEEN DEVELOPED THAT PROVIDES AUTOMATIC, ADAPTIVE, AND DYNAMICALLY CONFIGURABLE INTER-PROCESSOR COMMUNICATIONS AND IS COMPATIBLE WITH MOST COMMERCIALLY AVAILABLE STATE-OF-THE-ART COMPLEX INSTRUCTION SET COMPUTERS (CISC) AND REDUCED INSTRUCTION SET COMPUTERS (RISC). IN THIS INVESTIGATION, THE ARRAY COMMUNICATIONS CONTROLLER IS BEING IMPLEMENTED AS A COPROCESSOR SIMILAR TO A FLOATING POINT COPROCESSOR IMPLEMENTATION SO THAT INTER-PROCESSOR SYNCHRONIZED DATA TRANSFER COULD BE ACCOMPLISHED WITH A SINGLE IN-LINE INSTRUCTION. THIS METHODOLOGY WOULD GREATLY SIMPLIFY THE COMPLEXITY OF MULTI-PROCESSOR COMPUTER HARDWAREAND SOFTWARE. WHEN SUCCESSFUL, THIS INTER-PROCESSOR COMMUNICATIONS ARCHITECTURE WOULD PROVIDE AN AVENUE FOR DEVELOPMENT OF MULTI-PROCESSOR COMPUTERS FOR ADDRESSING LARGE SCALE STRATEGIC DEFENSE COMPUTING PROBLEMS, AND SIMPLER SOFTWARE FOR MULTI-PROCESSOR, REAL-TIME CONTROLLERS.