An Efficient Parallel SAT Solver Exploiting Multi-Core Environments
Award amount
$100,000Program and phase
SBIR · Phase IAward year
2009Award details
- Awarding agency
- National Aeronautics and Space Administration
- Branch
- Not reported
- Recipient company
- ARIES DESIGN AUTOMATION, LLC
- Proposal award date
- Not reported
- Contract end date
- Not reported
- UEI
- KHN1ZN6ALMV4
- Solicitation number
- Not reported
- Topic code
- Not reported
Research abstract
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- Design and Formal Verification of a Fault-Tolerant RISC-V Processor Core Augmented to Accelerate Image and Science Data Processing
- Design and Formal Verification of a RISC-V DSP for Space Communication
- Formal Verification of Interactions of the RTOS, Memory System, and Application Programs at the PowerPC 750 Binary Code Level
- Scalable Parallel Algorithms for Formal Verification of Software
- Scalable Parallel Algorithms for Formal Verification of Software
Research funding history
19 SBIR/STTR records share this UEI (2006–2022). Reported award amounts total $4,465,000. Reported amounts are not federal obligations.
Phases: Phase I, Phase II, Phase II – Direct to Phase II
Agencies: National Aeronautics and Space Administration, Department of Defense, Department of Energy, National Science Foundation, Department of Commerce