DEVELOPMENT OF HIGH BANDWIDTH FASTBUS DATA PREPROCESSING MODULES

THIS PROJECT WILL DEVELOP A FASTBUS PREPROCESSING MODULE DESIGNED TO PROVIDE A PROGRAMMABLE MEANS OF CALIBRATING AND REDUCING LARGE STREAMS OF DATA FROM RELATIVELY UNINTELLIGENT DIGITIZER MODULES IN A FASTBUS CRATE. THIS THIS PROCESSOR WILL BE ABLE TO ELIMINATE DATA FROM EMPTY CHANNELS, PERFORM CHANNEL-BY-CHANNEL CORRECTIONS (E.G., POLYNOMIAL OR PIECEWISE LINEAR) TO SIGNIFICANT DATA, AND REDUCE DATA BY CHARACTERIZING STREAMS OF SIGNIFICANT DATA, BY A FEW MEANINGFUL PARAMETERS (E.G.,REDUCING 50 SAMPLES OF PULSE HEIGHT ON A DRIFT CHAMBER WIRE TO PULSE CHARGE AND ARRIVAL TIME OF ONE OR MORE PARTICLES). THE DESIGN GOAL IS FOR A COMPLETE MODULE TO HANDLE STREAMS OF DATA OF OF ABOUT 5 MEGABYTE/S AVERAGE INPUT RATE AND 50 MEGABYTE/S PEAK INPUT RATE (I.E., 10% INPUT DUTY CYCLE FOR MINIMAL DEAD TIME), WHILE PROVIDING A MINIMUM PROCESSING CAPACITY OF 5 INSTRUCTION/BYTES OF INPUT DATA OR 25 MILLION INSTRUCTION/S (MIPS). THEE SYSTEM SHOULD ALSO PROVIDE FOR MODULAR EXPANSION OF THE PROCESSING CAPACITY TO 100 MIPS. THE HARDWARE UTILIZES A VERY LARGE SCALE INTEGRATION (VLSI) FASTBUS INTERFACE DEVELOPED UNDER A PREVIOUS SBIR CONTRACT. PROCESSING POWER IS PROVIDED IN ONE OF THREE MANNERS (TO BE INVESTIGATED): (1) AN ARRAY OF COMMERCIAL VLSI PARALLEL-PROCESSING ARRAY ELEMENTS FEATURING INTEGRATEDON-CHIP RAM AND SERIAL I/O CHANNELS; (2) AN ARRAY OF LATEST GENERATION 16- OR 32-BIT MICROPROCESSORS WITH MINIMAL RAM, ROM, AND I/O CAPACITY/CHIP; OR (3) A SINGLE, HIGH- PERFORMANCE SPECIALIZED PIPELINED PROCESSOR CONSTRUCTED FROM ECL (EMMITER COUPLED LOGIC) BIT SLICES. IT SHOULD BE EMPHASIZED THAT THE PROCESSING SECTION OF THIS MODULE IS INTENDED TO EXECUTE RELATIVELY STATIC ROM-BASED ALGORITHMS.