A 1280x1024 Indium Gallium Arsenide Photodiode Array with 12 ¿m Pitch

Systems & Processes Engineering Corporation (SPEC) proposes the Hyper-ASIC Program to impact hyperspectral imaging and fast parallel processing of algorithmic data for non-destructive inspection, smart munitions, target identification and classification,and battlefield damage assessment. Hyper-ASIC penetrates to the heart of the commercial semiconductor market with a unique product strategically placed among the field programmable gate array (FPGA), digital signal processor (DSP), and traditional singleapplication, non-adaptive ASIC chipsets. The innovation of the research is the uniquely adaptive architecture featuring a Mathematical Matrix Algorithm Processor (MMAP) consisting of Dynamically Configurable (Mathematical) Macros (DCM) pipelined inhardware to support high speed parallel processing of data under software control. Hyper-ASIC is optimized for 16 bit performance and can be expanded as requirements dictate. Detailed analysis of the system reveals that 16 bit (and future expansion)performance is supported without truncation of data during internal computations. Hyper-ASIC has exceptional system performance metrics - frame dimensions of 1024 pixels for both X & Y dimensions, spatial pixel resolution of 16 bits, data rate of 32 Gbpssupporting 5 channels parallel processing, algorithms include