Specification Interfaces for Larch/VHDL Designs

This project will define and develop specification techniques for hardware designs eventually targeted for VHDL implementation. The specification techniques may be graphical or textual and will interface with the Larch/VHDL verification system. The specification techniques will be based on current state of the art CAD techniques for designing hardware. The specification techniques will provide a front-end user interface that generates formal specifications in a mathematical notation and VHDL designs suitable for actual hardware development. The combination of mathematical specification and VHDL design output will be suitable for use in the Larch/VHDL verification tool to verify the correctness of the hardware design. The VHDL designs themselves will be suitble input to a CAD system capable of carryuing out the remaining hardware implementation. The phase I effort will consist of three tasks. The first task is to identify suitable domains, such as digital signal processor design or finite state controller design, for which suitable front-end specification techniques can be developed. The second task will focus on one of these domains and define a system arthitecture for the specification interface tool. Finally, a prototype of the specification interface tool will be developed as a proof of concept.