FAULT-TOLERANT WAFER SCALE INTEGRATION

THIS PROGRAM REPLACES THE CONVENTIONAL PASSIVE INTERCONNECT SUBSTRATE USED IN MULTI-CHIP MODULES WITH AN ACTIVE SILICON SUBSTRATE. THIS APPLICATION USES THE ACTIVE SUBSTRATE (ASIC) TO IMPLEMENT A FAULT TOLERANT MEMORY SYSTEM. THE SUBSTRATE PROVIDES EDAC, AUTOMATIC SEU SCRUBBING, MEMORY MAPPING AND RECONFIGURATION, SPARES MANAGEMENT, SYSTEM I/O POWER CONTROL AND SELF TEST TO A 3-D STACKED MEMORY MODULE. THE SUBSTRATE IS ITSELF FAULT TOLERANT THROUGH THE USE OF SELF-CHECKING RECONFIGURABLE REDUNDANT CIRCUITS. USING CONVENTIONAL 1 MBIT SRAMS, AN 80 MBIT MEMORY (32 MBIT DATA, 8 MBIT EDAC, 40 MBITS SPARE) WITH >.999 RELIABILITY OVER A 10-YEAR MISSION LIFE CAN BE PACKAGED IN 0.15 CUBIC INCH, A DENSITY IMPROVEMENT OF OVER 2 ORDERS OF MAGNITUDE OVER A PLANAR HDI ON DEM-E MODULE APPROACH, WITH A SIMILAR INCREASE IN RELIABILITY, JUNCTION TEMPERATURE RISE IS DEGREE C/WATT. MULTIPLE MODULES PACKAGED IN A SINGLE HYBRID ACHIEVE HIGHLY DEPENDABLE MEMORY SYSTEMS. PRODUCTION COST OF THESE MODULES IS PROJECTED TO BE SIMILAR TO CONVENTIONAL MEMORY SYSTEMS.