RADIATION-HARD FERROELECTRIC-ON-GAAS RANDOM ACCESS MEMORIES FOR MISSILES AND/OR SPACECRAFT

A SYSTEMATIC STUDY OF THE SPUTTERING TECHNOLOGY AND INTERFACE METALLURGY FOR LEAD ZIRCONATE TITANTE/PLATIUM/GALLIUM-ARSENIDE (PZT/PT/GAAS) IS BEING UNDERTAKEN THAT IS EXPECTED TO PERMIT LARGE, RAD-HARD, NONVOLITLE FERROELECTRIC RANDOM ACCESS MEMORIES (RAMS) TO BECONSTRUCTED. EXISTING PROTOTYPE PZT MEMORY DEVICES HAVE BEEN FABRICATED THUS FAR ONLY ON COMPOSITE METAL-OXIDE SEMICONDUCTOR (CMOS) SILICON DECODERS AND EXTENSION OF THE TECHNOLOGY TO RAD-HARD SUBSTRATES SUCH AS GAAS IS URGENT. AN EXPERIMENTAL STUDY OF UNDECODED PZT/PT/GAAS ARRAYS IS BEING CONDUCTED TO DETERMINE PROCESSING STEPS REQUIRED TO FABRICATE COMMERCIALLY VIABLE RAD-HARD MEMORIES. SPECIFICALLY, GAAS SUBSTRATES ARE BEING USED THAT HAVE TEST PATTERNS OF FERROELECTRIC CAPACITORS OF SIZED FROM 2 TO 250 MICRONS DEPOSITED ON THEM WITH PLATIUM ELECTRODES WITH AND WITHOUT POLY LAYERS. COMPATIBILITY OF GAAS/PT, GAAS/POLY-SI/PT, AND GAAS/PZT, GAAS/POLY-SI/PZT INTERFACES ARE BEING TESTED WITH RESPECT TO MECHANICAL ADHESION AND ELECTRICAL SWITCHING CHARACTERISTICS. TOGETHER WITH PROCESSING PARAMETER. ANNEALING STUDIES ARE BEING UNDERTAKEN. PT ELECTRODES ARE BEING ALLOYED TO MAXIMIZE ADHESION. MULTIPLE METAL LAYERS ARE BEING EXPERIMENTED WITH AS AN ALTERNATIVE TO POLYSILICON. FABRICATION AND TESTING OF A PROTOTYPE, FULLY DECODED 256-OR 512 PZT-ON-GAAS CMOS RAM WOULD BE PERFORMED IN A LATER PHASE.