COMPACT HIGH DENSITY ANALOG TO DIGITAL READOUT CIRCUITS FOR SILICON MICROSTRIP DETECTOR ARRAYS

THE CURRENT IMPLEMENTATION OF READOUT CIRCUITS FOR SILICON MICROSTRIP DETECTOR ARRAYS INVOLVES THE USE OF ONE AMPLIFIER AND ONE COMPARATOR DETECTOR. AS THE DENSITY OF THE ARRAYS INCREASES, THE COMPLEXITY, SIZE, POWER DISSIPATION, AND COST OF THIS APPROACH INCREASE AND MAY BECOME PROHIBITIVELY HIGH. A NOVEL READOUT CIRCUIT THAT ACCOMPLISHES THE SAME FUNCTION WHILE ELIMINATING THE AMPLIFIERS AND SIGNIFICANTLY IMPROVING THE POWER DISSIPATION AND DENSITY IS THE GOAL OF THIS PROJECT. THE APPROACH IS BASED ON USING SUPERCONDUCTING QUANTUM INTERFERENCE DEVICES (SQUIDS) TO DETECT THE OUTPUT OF THE SILICON STRIP DETECTORS. THE VOLTAGE SIGNAL FROM THE SQUID APPEARS AS A DIGITAL SIGNAL THROUGH THE JOSEPHSON VOLTAGE-TO-FREQUENCY RELATION. THE STRING OF SINGLE FLUX QUANTUM (SFQ) PULSES GENERATED BY THE SQUID IS THEN SYNCHRONIZED, COUNTED, AND READ OUT USING SUPERCONDUCTING ELECTRONICS CIRCUITS. THE COMPLETE READOUT CIRCUIT IS IMPLEMENTED MONOLITHICALLY ON A SINGLE SUBSTRATE. THE METHOD AMOUNTS TO A COMPLETE INTEGRATED ANALOG TO DIGITAL CONVERTOR (ADC) WITH PIPELINE STORAGE. THE ADC WILL HAVE A FULL SCALE RANGE OF 0 TO 640 NA. THIS SENSITIVTY WILL ELIMINATE THE NEED FOR PREAMPLIFERS, AND PROVIDE A DIGITIZED OUTPUT OF THE NUMBER OF ELECTRONS OVER THE SAMPLE INTERVAL THE NUMBER OF ELECTRONS OVER THE SAMPLE INTERVAL WITH 250 ELECTRONS RESOLUTION. THE ADC DESIGN IS COMPACT (LESS THAN ONE MM(2)) AND EXTREMELY LOW-POWER (LESS THAN ONE MW). THIS WILL ALLOW THE INTEGRATION OF 500,000 READOUT CHANNELS WITH THE SAME NUMBER OF SILICON MICROSTRIP DETECTORS. TO SIMPLIFY THE INTERFACE, A SERIAL READOUT METHOD ALLOWING MULTIPLE CHIPS TO BE READ OUT ON A SINGLE HIGH WIRE IS PLANNED. ALTERNATIVELY, THE ADC CAN BE INTEGRATED WITH A SHIFT REGISTER-BASED FIRST-IN FIRST-OUT STORAGE ON-CHIP FOR LATER READOUT. SUPERCONDUCTING LOGIC CAN ALSO IMPLEMENT ONE OR MORE DIGITAL COMPARATORS PROVIDING A BINARY HIT/NO HIT DIGITAL OUTPUT, AND THE THRESHOLD DATA CAN BE LOADED BY A SINGLE SERIAL WIRE. PHASE I WILL DEMONSTRATE THE FEASIBILITY OF THE APPROACH BY DEMONSTRATING THE VOLATAGE-TO-FREQUENCY CONVERSION OF THE OUTPUT OF A SQUID. IN PHASE II, A COMPLETE READOUT CHANNEL DEMONSTRATING THE REQUIRED SENSITIVITY WILL BE PRODUCED.