DEVELOPMENT OF 32 BIT SINGLE BOARD COMPUTER SYSTEMS IN FASTBUS PACKAGING

A FASTBUS PACKAGED 32 BIT COMPUTING SYSTEM INCLUDING BOTH FASTBUS HARDWARE AND SOFTWARE FOR PROGRAM DEVELOPMENT, DEBUGGING, AND RUN-TIME SUPPORT WILL BE DEVELOPED. THE HARDWARE WILL FEATURE A 32 BIT CPU, PREFERABLY IMPLEMENTING THE DEC VAX ARCHITECTURE, BUT NOT IMMEDIATELY EXCLUDING CURRENT OFFERINGS FROM INTEL, MOTOROLA, HEWLETT-PACKARD, OR NATIONAL SEMICONDUCTOR, PLUS ON-CARD MAIN MEMORY IN THE RANGE FROM .5 TO 2.0 MEGABYTES, AND NECESSARY PERIPHERALS INCLUDING A FASTBUS INTERFACE. SOFTWARE WILL INCLUDE CODE DEVELOPMENT AND DEBUGGING TOOLS DESIGNED TO RUN ON A DEC VAXHOST, PLUS DOWNLINE LOADERS AND RUN-TIME SUPPORT DESIGNED TOALLOW COMMUNICATION BETWEEN THE TARGET PROCESSOR AND BOTH THE HOST AND OTHER TARGET PROCESSORS.