DIGITAL RF MEMORY MODULATOR

SYSTEMS & PROCESSES ENGINEERING CORPORATION (SPEC) HAS DEVELOPED TWO ALTERNATIVE DESIGNS THAT MEET OR EXCEED THE FUNCTIONAL AND TIMING REQUIREMENTS OF THE DIGITAL MODULATOR. THE FIRST IMPLEMENTATION IS CENTERED AROUND A HIGH PERFORMANCE 1.0 UM CMOS APPLICATION SPECIFIC INTEGRATED CIRCUIT (ASIC), DESIGNED AND SIMULATED AT SPEC, THAT USES EIGHT 8-BIT MULTIPLIERS OPERATING IN PARALLEL TO PROVIDE THE 250 MHZ THROUGHPUT REQUIRED BY THE MEMORY SYSTEM. ONE ASIC IS REQUIRED FOR EACH I AND Q CHANNEL, ALONG WITH EXTERNAL INTERFACE LOGIC TO THE DIGITAL RF MEMORY AND DIGITAL-TO-ANALOG CONVERTER. THE SECOND IMPLEMENTATION PROPOSED IS BASED ON SPEC'S GAAS DATAPATH COMPILER TECHNOLOGY DEVELOPED UNDER CONTRACT TO DARPA. IN THIS HIGHLY INTEGRATED DESIGN, SPEC PROPOSES TO IMPLEMENT THE COMPLETE DIGITAL RF MEMORY SYSTEM (EXCLUDING ADCS, DACS, AND RAM) IN A SINGLE GAAS INTEGRATED CIRCUIT. THE GAAS ASIC WOULD CONTROL THE ADCS, DACS, AND RAM, AND MODULATE BOTH THE I AND Q CHANNELS BY MULTIPLYING THE DELAYED RF SIGNALS BY INDEPENDENTLY SYNTHESIZED WAVEFORMS. EITHER INTEGRATED CIRCUIT APPROACH CAN MEET THE 100 NSEC MAXIMUM SIGNAL DELAY REQUIREMENT, OPERATE AT AN EFFECTIVE THROUGHPUT OF 250 MHZ OR BEYOND, AND PROVIDE EIGHT OR MORE BITS OF RESOLUTION.