Handheld Laser-Based Sensor for Remote Detection of Gas Leaks

Not Available A Field Programmable Gate Array (FPGA) architecture is proposed that is specifically designed for digital signal processing (DSP) applications. It is called the PDPA (Programmable Data Path Array) architecture and is characterized by the following features: specific support for data path functions, programming of logic elements in groups of 8, programming of routing switches in groups of 8, significant reduction of routing to logic ratio, architectural provisions for vector processing and pipelining, and provisions for context switching (logic and routing) through register files. The PDPA allows logic and routing resources to be programmed in groups having a size equal to the bus width, reducing the number of programming bits needed to implement user functions. This specialization also reduces the routing to logic ratio permitting more computational logic resources. Vector processing and switching of both logic and routing are naturally incorporated by storing the programmation in register files. Because of the tight data coupling between computing elements, we fully expect the PDPA to perform data path signal processing functions at clock speeds of 50 MHz.