High Resolution ADC for Nuclear Physics Experiments

Alphacore proposes to develop a 64-channel, 16-bit, 4GS/s Digitizer ASIC in this Nuclear Physics (NP) SBIR program. A critical requirement is to provide seamless output interface for Streaming Mode, as well as Triggered Mode. Streaming Mode interface requires high data bandwidth with low-power. Alphacore has a siicon-proven, low-power SerDes IP demonstrated in the selected TSMC 28nm process and this SerDes is optimal to provide the Streaming Mfunctionality from the ASIC to an FPGA. Alphacore is about to finalize the Backend 12b, 4GS/s ADC layout in TSMC 28nm process and then send it to be fabricated in December 2024. It is based on our GF22FDX 22nm A12B5G core that has been Alphacore’s biggest Commercial Success (>$5M revenues so far). This ADC will be the “Back-End SAR ADC” in the Proposed HybridSAR-Pipeline ADC. The design and tapeout for the TSMC 28nm core have been covered from Alphacore’s internal IRAD funds. The ADC will be evaluated in the proposed Phase I, followed by optimizations. We will also apply “Supervised ML Calibration” on it in Phase I. Objective 1: Evaluate the taped out 12-bit, 4GSPS TSMC 28nm ADC Objective 2: Design 1-channel, 16-bit, 4GS/s digitizer Objective 3: Design 64-channel, 16-bit, 4GS/s digitizer that has both Streaming and Triggered Modes Objective 4: Design Evaluation Boards optimized for NP researchers The main commercial product to result in this DOE SBIR Phase I program will be a high resolution (16bit ENOB) Analog-to-Digital Converter (ADC). The market opportunity of this product is extremely potent based on both statistics from research analysts, as well as the insights from subject matter experts in this market, along with Alphacore’s own experience as a leading data converter IP provider for analog and mixed signal blocks, including high performance data converters.