SBIR/STTR Research Award
Gigascale, Mixed-Signal, Integrated System Verification
Award amount
$375,000Program and phase
SBIR · Phase IIAward year
2002Award details
- Awarding agency
- Department of Defense
- Branch
- Defense Advanced Research Projects Agency
- Recipient company
- FTL Systems, Inc.
- Proposal award date
- Not reported
- Contract end date
- Not reported
- UEI
- MCJSGW2W4C76
- Solicitation number
- Not reported
- Topic code
- Not reported
Research abstract
"Next-generation military systems integrating one billion or more transistor-equivalent digital, analog, and high frequency components may be iteratively verified more than 100 times as rapidly by technology developed and evaluated in this project.Specifically FTL Systems extends the VHDL-AMS design language (along with mirrored Verilg-AMS functionality) to include distributed elements (with partial differential equation and finite element models) as well as coupled time and frequency domainmodeling. Tool implementations (in conjunction with other efforts) harness shared-memory multiprocessor, clustered shared-memory multiprocessors and unique accelerators."
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- Compensation of Superconducting ADC for Improved Accuracy
- Agile, Robust and Concurrent Cross-Correlation From HF Through Ka Band
- Streaming Data Capture, Processing and Network Access from Array of Superconducting Analog to Digital Converters
- Low-Jitter/Skew, Tunable, High Bandwidth Clock Generation and Distribution into Cyrogenic Environments
- Agile, Robust and Concurrent Cross-Correlation From HF Through Ka Band
Research funding history
11 SBIR/STTR records share this UEI (1997–2010). Reported award amounts total $3,479,765. Reported amounts are not federal obligations.
Phases: Phase I, Phase II
Agencies: Department of Defense