Next Generation CAD Tools for Gigascale Integrated Mixed Signal System on a Chip

This proposal demonstrates the feasibility of top-down, VHDL-based verificationof gigascale, integrated, mixed-signal system-on-a-chip for military applications.Building on FTL Systems' unique parallel-compile, parallel-execute HDLcompiler/simulator, this effort introduces novel analog solver, iterativeoptimization, parallel processing and hardware acceleration technology. Thesenovel technologies enable the gigascale, mixed-signal designer to optimizedesign parameters such as integration density, cross-talk, interconnect latency,power/thermal management and fault-tolerance using VHDL, VHDL-AMS, andVHDL-RF/MW with a 100x to 1000x verification time reduction. Since verificationaccounts for more than half the design cycle time, a 10x to 100x reductionin design cycle time results. The anticipated Phase II design targetuses 3-D die stacking technology to shrink an avionics processorand associated I/O processing complex by more than 10x with a firstpass correct-functionality objective.Ability to accurately and rapidly verify giga-scale, mixed-signaldesigns conveys key advantages for integrated avionic processorcomplexes (such as those developed for the JSF), commercial wirelesscommunication devices (such as those developed by the BluetoothConsortium) and for integrated electronic and photonic systems(such as medical image processing systems). These advantagesinclude denser packaging, lighter weight, lower-powerconsumption, higher reliability, lower design cost andlower production costs in the context of gigascale,high-frequency, mixed-signal systems. FTL Systems hasthe commercial relationships to rapidly impact allthree of these application areas with commercial products.