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Award details
- Awarding agency
- Department of Defense
- Branch
- Army
- Recipient company
- Systems & Processes Engineering Corporation
- Proposal award date
- Not reported
- Contract end date
- Not reported
- UEI
- M5JVFYWW75P1
- Solicitation number
- Not reported
- Topic code
- Not reported
Research abstract
SYSTEMS & PROCESSES ENGINEERING CORPORATION (SPEC) HAS DEVELOPED A DIGSYSTEMS & PROCESSES ENGINEERING CORPORATION (SPEC) HAS DEVELOPED A DIGITAL GAIN CONTROLLED INSTRUMENTATION AMPLIFIER ASIC SYSTEM DESIGN FOR ITAL GAIN CONTROLLED INSTRUMENTATION AMPLIFIER ASIC SYSTEM DESIGN FOR INTERFACING A TRANSDUCER TO AN ANALOG-TO-DIGITAL CONVERTER. THIS ASICINTERFACING A TRANSDUCER TO AN ANALOG-TO-DIGITAL CONVERTER. THIS ASIC BUILDING BLOCK WILL FULFILL THE ARMY'S REQUIREMENTS FOR GENERIC MIXED BUILDING BLOCK WILL FULFILL THE ARMY'S REQUIREMENTS FOR GENERIC MIXED MODE INTEGRATED CIRCUITS FOR DATA CONDITIONING THE PROPOSED GENERIC M MODE INTEGRATED CIRCUITS FOR DATA CONDITIONING THE PROPOSED GENERIC MIXED MODE ASIC CONSISTS OF A PROGRAMMABLE GAIN CONTROLLED AUTO-ZERO INIXED MODE ASIC CONSISTS OF A PROGRAMMABLE GAIN CONTROLLED AUTO-ZERO INSTRUMENTATION AMPLIFIER, AN ANTI-ALIASING FILTER, A LOW OUTPUT IMPEDANSTRUMENTATION AMPLIFIER, AN ANTI-ALIASING FILTER, A LOW OUTPUT IMPEDANCE BUFFER, AND POWER DOWN CIRCUIT. IN THE PHASE I PROGRAM, SPEC PROPOSCE BUFFER, AND POWER DOWN CIRCUIT. IN THE PHASE I PROGRAM, SPEC PROPOSES TO DESIGN, LAYOUT AND SIMULATE AN ASIC DIGITAL GAIN CONTROLLED INSTES TO DESIGN, LAYOUT AND SIMULATE AN ASIC DIGITAL GAIN CONTROLLED INSTRUMENTATION AMPLIFIER TARGETABLE TO CMOS TECHNOLOGIES. THE PERFORMANCRUMENTATION AMPLIFIER TARGETABLE TO CMOS TECHNOLOGIES. THE PERFORMANCE OF CMOS ANALOG CIRCUITS IS COMPARABLE TO THEIR CONVENTIONAL BIPOLAR E OF CMOS ANALOG CIRCUITS IS COMPARABLE TO THEIR CONVENTIONAL BIPOLAR COUNTERPARTS, WHILE MAINTAINING THE ADVANTAGE OF LOWER POWER DISSIPATICOUNTERPARTS, WHILE MAINTAINING THE ADVANTAGE OF LOWER POWER DISSIPATION. SPEC'S ASIC DESIGN CENTER HAS AN EXPANSIVE CAE ENVIRONMENT FOR TAON. SPEC'S ASIC DESIGN CENTER HAS AN EXPANSIVE CAE ENVIRONMENT FOR TARGET MULTIPLE IC TECHNOLOGIES AND FOUNDRIES FOR FUTURE IMPLEMENTATIONSRGET MULTIPLE IC TECHNOLOGIES AND FOUNDRIES FOR FUTURE IMPLEMENTATIONS OF THE GENERIC MIXED MODE ASIC'S. OF THE GENERIC MIXED MODE ASIC'S.
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
Research funding history
206 SBIR/STTR records share this UEI (1987–2025). Reported award amounts total $59,199,771. Reported amounts are not federal obligations.
Phases: Phase I, Phase II, Phase II – Direct to Phase II
Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Homeland Security, Department of Energy, Environmental Protection Agency, National Science Foundation
Agency intelligence
Department of Defense
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