GAAS RISC ARRAY PROCESSOR

SYSTEMS & PROCESSES ENGINEERING CORPORATION (SPEC) HAS DEVELOPED AN INNOVATIVE ARRAY PROCESSOR ARCHITECTURE FOR COMPU- TING FOURIER TRANSFORMS AND OTHER COMMONLY USED SIGNAL PROCESSING ALGORITHMS. THIS ARCHITECTURE IS DESIGNED TO EX-TRACT THE HIGHEST POSSIBLE ARRAY PERFORMANCE FROM STATE-OF- THE-ART GAAS TECHNOLOGY. THE ARCHITECTURAL DESIGN FEATURES A HIGH PERFORMANCE RISC PROCESSOR IMPLEMENTED IN GAAS, ALONGALONG WITH A FLOATING POINT COPROCESSOR AND A UNIQUE ARRAY COMMUNICATIONS COPROCESSOR, ALSO IMPLEMENTED IN GAAS. THE ARCHITECTURE INCLUDES VERY HIGH SPEED, LOW GATE COUNT BIT-SERIAL ARITHMETIC AND COMMUNICATION UNITS IN THE FLOAT- ING POINT AND COMMUNICATION COPROCESSORS, RESPECTIVELY. UTILIZING THE VERY HIGH SPEED OF GAAS, CURRENTLY WITH CLOCK RATES IN EXCESS OF 1 GHZ, BIT-SERIAL UNITS CAN BE USEDTO FORM THE CORE OF COMPLEX ARITHMETIC AND COMMUNICATIONS UNITS. A BIT-SERIAL VLSI ARCHITECTURE IS, IN FACT, IDEAL FORIMPLEMENTATION OF THE COMMUNICATION LINKS BETWEEN PROCESSORSTHE OBJECTIVE OF THE PHASE II PROGRAM IS TO DESIGN AND SIMU-LATE AN ARRAY PROCESSOR UTILIZING HIGH PERFORMANCE GAAS RISCPROCESSORS AND COPROCESSORS.