SBIR/STTR Research Award

Reconfigurable Processors for Software Protection

Award identifier 27f99b2289a9b4e7b9e381f5746f1564c577c3cc42c6621cf54ccc4da344d852Awarding agency Department of Defense · Air Force

Award amount

$99,948

Program and phase

SBIR · Phase I

Award year

2003

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Award details

Awarding agency
Department of Defense
Branch
Air Force
Recipient company
SYSTRAN FEDERAL CORP.
Proposal award date
Not reported
Contract end date
Not reported
UEI
KN47KKNMWKQ9
Solicitation number
Not reported
Topic code
Not reported

Research abstract

Systran Federal Corporation is proposing to solve the software protection problem by developing a reconfigurable processor, in which the opcode instruction set could be changed. We are proposing the development of the tools and the mechanisms that arerequired for a reconfigurable processor with a variable opcode instruction set, to defeat any effort to reverse engineer the protected software. Each time source code is compiled targeting a system, the software tools, such as, the assembler used togenerate the executable code, should know the instruction set that is used in that particular system. When the Field Programmable Gate Array (FPGA) design tools are available the instruction set could be modified and a new instruction set incorporated tothe reconfigurable processor. The processor will be embedded in the FPGA such that the pins cannot be accessed using hardware.We are also proposing another method based on encrypting the executable code. In this method, we propose to encrypt the executable code that is targeted to be executed on the reconfigurable processor. The instruction set of the reconfigurable processorwould not be reprogrammable. However, the executable code is assumed to be encrypted using a set of keys of a known length. The instructions will be decrypted using the set of keys that is unique to each processor. The decryption module and the set of keysare embedded at design time in the FPGA and are not visible by software. The keys are assumed to be of adequate length such that it will require an enormous amount of time to do a comprehensive analysis when the decryption algorithm is known. Thedecryption module and the processor would be embedded in the FPGA such that the pins cannot be accessed using hardware. The main benefit of this effort would be that an executable program software could be protected from reverse engineering using a variable opcode instruction set reconfigurable processor.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

105 SBIR/STTR records share this UEI (1983–2008). Reported award amounts total $24,877,169. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense, Department of Commerce, National Aeronautics and Space Administration, Department of Energy, National Science Foundation

Agency intelligence

Department of Defense

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