SBIR/STTR Research Award

Stacked Adaptive Computing Module

Award identifier 4a0b94132344dfa1fc0ee679b3fcd7dcdac8b308ed8c8e1ac1a016960364eb82Awarding agency Department of Defense · Air Force

Award amount

$99,569

Program and phase

SBIR · Phase I

Award year

2001

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Award details

Awarding agency
Department of Defense
Branch
Air Force
Recipient company
Irvine Sensors Corporation
Proposal award date
Not reported
Contract end date
Not reported
UEI
QS98AJNH3J28
Solicitation number
Not reported
Topic code
Not reported

Research abstract

ISC proposes to develop an adapative computing module using stacked commercially available, programmable gate arrays (FPGAs), processors and memories to provide a universal hardware commonality which will ease system design and delay obsolescence. Itwill also alleviate the need for ASIC processors and controllers in many applications, as RISC versions of high-end microprocessors can also be emulated. Using currently available FPGAs, it will be even be possible to reconfigure on-the-fly, such thatsoftware for different platforms may be run on the same system, with the transitions being transparent to the user. Projecting a step further, developers may be able to customize the behavior of the processor to optimize for a specific complex task, ormix and match the best of multiple processors, all within software. ISC is in a unique position to develop such a system. Using a novel 3D stacking method, we can turn a prototype system of COTS components into a monolithic device, bypassing the ICdesign and wafer manufacturing steps. This approach has the added benefit that we can readily upgrade the system as the component COTS technologies are advanced. The complexity and the performance improvement provided by stacking will allow the stackedmodules to have performance similar to monolithic ASICs.This module can serve the needs of data mining and data processing applications. Developed technology can be applied as a service to OEM and other industrial or governmental institutions in need of along term solution to changing processor needs for a large variety of applications.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

186 SBIR/STTR records share this UEI (1983–2021). Reported award amounts total $64,762,800. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Health and Human Services, National Science Foundation, Department of Homeland Security

Agency intelligence

Department of Defense

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