Superconducting Logic for Wideband Beamforming

Current beamforming systems limited to digital processing at a basebands of typically less than 1OOMHz, restricted by 5OOMS/s Analog to Digital Convertors (ADC) and 1OOMS/s Digital Signal processors. HYPRES proposes a promising new way to realize a digital beamformer based on true time delay elements and capable of ultra-wide bandwidth operation combined with arbitrarily large array size by using recently developed superconducting RSFQ digital technology. HYPRES has demonstrated the key elements required for a digital system, the operation of an 8-bit 2OGS/s ADC capable of digitizing 1-l8GHz input signals and superconducting logic capable of pipelined arithmetic functions at clock rates in excess of 2OGHz. The digital wideband beamforming system proposed is required to perform the delay, multiply and sum functions necessary to implement the beamforming algorithm. The Phase l objective is to demonstrate the high-speed operation of the critical components of an extendible wideband digital beamforming system. Toward this goal, HYPRES will implement and test a 64-bit Variable-Length Shift Register and a Parallel Multiplier design operating at 10 to 2OGHz. HYPRES proposes in Phase II to develop a digital wideband Beamforming system. The proposed system would use a wideband ADC operating at up to 2OGS/s for a 1OGHz instantaneous bandwidth baseband. The system would use multiple copies of a single IC with a fast ADC and beamforming section. These ICs would be cascadable to any size array. For implementation of large spatial arrays, the IC would have an optical input, this would allow for many widely separated antennae. The IC would be 1cm x 1cm and dissipate less than IOOmW, a complete 64 channel beamforming front-end system could be implemented on a single 6" substrate.