SBIR/STTR Research Award

Very High Speed Integrated Circuit Hardware Description Language (VHDL) Models for Backplane Open System

Award identifier f079ad49959d472291ce1478c2c32ed83af054cce20dbcda3ea47f7d7160a249Awarding agency Department of Defense · Air Force

Award amount

$99,129

Program and phase

SBIR · Phase I

Award year

1998

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Award details

Awarding agency
Department of Defense
Branch
Air Force
Recipient company
RAM LABORATORIES
Proposal award date
Not reported
Contract end date
Not reported
UEI
MNKGBEH2M2V3
Solicitation number
Not reported
Topic code
Not reported

Research abstract

Because of the large costs associated with developing state-of-the-art systems, today's military has turned toward developing systems based on backplane open architecture standards. Developing systems based on such standards allows for the inclusion of commercial off-the-shelf components in the development of military systems. However, existing models which promote the top-down design and analysis of such systems are lacking, if not non-existent. The Phase I effort will lay the groundwork for the development of hardware models to support top-down development of backplane open system architectures. This effort will define the types of modeling paradigms, modeling targets, and bus protocols which will be required to support backplane open architecture design at various levels of design detail.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

56 SBIR/STTR records share this UEI (1998–2024). Reported award amounts total $16,417,810. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense, Department of Homeland Security

Agency intelligence

Department of Defense

Back to SBIR/STTR Research Awards

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