Secure High-Assurance Aberdeen Architecture RISC-V Complier and Softcore using Aberdeen Architecture (SHAAARCS)

Modern cybersecurity principles emphasize a layered defense approach, incorporating least privilege and continuous monitoring to ensure robust protection of systems and data. Key practices such as continuous verification and authentication enhance security from the operating system level up to the enterprise level. However, current microprocessor architectures, optimized for performance rather than security, lack the ability to implement these practices at the hardware level during instruction execution. Spectre and Meltdown are prime examples that highlight vulnerabilities affecting a wide range of processors, including those from Intel, AMD, and ARM. These vulnerabilities allow threat actors to exploit speculative execution and branch prediction features to access sensitive data. The Aberdeen Architecture recognizes the need for continuous verification and is a proposed concept that uses hardware state machines to enforce four main security policies at the hardware level: (1) instruction execution, (2) page memory access, (3) control flow integrity, and (4) data flow integrity.  Each corresponding state machine implements its security policy independently of the processor execution pipeline in two pieces:  a local policy to set strict limits on individual instructions alongside a global policy to limit propagation of process faults. This two-stage security policy architecture provides an efficient trade-off between fine-grained access control at the instruction level and performance impacts of the security mitigations. Previous work has demonstrated the effectiveness of this architecture in addressing software vulnerabilities and this proposal will evaluate the feasibility of realizing this core in an actual processor by incorporating one specific element of the Aberdeen Architecture, mediation of instructions, into an existing open source RISC-V processor (e.g. RocketChip).  In addition to integrating instruction execution monitoring, this study will also conduct a study of the available RISC-V toolchains to enable a two-level tagged architecture. The toolchain survey will identify the necessary changes for user specification of tags and security policies and evaluate which toolchain would be best suited for this architecture. By demonstrating a processor with an integrated hardware state machine and creating a plan for toolchain modification, this effort will provide a roadmap for realization of the complete Aberdeen architecture and better system security.