CAD Conversion Tools for VHDL-AMS Library Generation

This project enables and incentivizes adaptation of IEEE Draft Standard 1076.1 (VHDL AMS) by mixed signal (analog/digital) engineers by providing a feasible, low risk migration path for existing SPICE like models (equivalence), then adds capability beyond that of SPICE (incentive). Specific work items include "black box" VHDL AMS source code generator technology, SPICEcompatible analog solver technology for VHDL AMS simulation, differencing technology enabling comparison of two closely related VHDL AMS models, and modeling technology to realize a VHDL AMS equivalent of SPICE 3 device models in VHDL AMS.