HIGH PERFORMANCE SUPERCONDUCTING FLUX-QUANTIZING A/D CONVERTERS USING MULTIBIT DIFFERENTIAL CODE FRONT END & RSFQ LOGIC BASED DECIMATION FILTER

HYPRES PROPOSES A PROGRAM TO RESEARCH, DEVELOP AND DEMONSTRATE A NEW CLASS OF HIGH-PERFORMANCE SUPERCONDUCTING A^D CONVENERS (ADCS) BASED ON COUNTING SINGLE MAGNETIC HUX QUANTA, HIGH-SPEED DIFFERENTIAL CODING, AND DECIMATION FILTERING. THE AD CS WILL MAINTAIN A UNIQUE BANDWIDTH-TO-ACCURACY TRADE-OFF RATIO OF 1.5 EFFECTIVE BITS PER FACTOR OF 2 BANDWIDTH (BW) REDUCTION (INSTEAD OF THE USUAL 1 BIT). THIS IMPROVEMENT IS DUE TO AN ULTRAFAST DECIMATION FILTER USING RECENTLY DEVELOPED RAPID SINGLE FLUX QUANTUM (RSFQ) LOGIC/MEMOIY ELEMENTS CAPABLE OF IOOGHZ OPERATION. THE PROGRANGOAL IS TO REPLACE THE SIMPLE 2-BIT QUANTIZER FRONT END OF THE ADC WITH A MULTI-BIT SOUID WHEEL DESIGN, YIELDING 3 EXTRA BITS OF RESOLUTION FOR THE SANE BANDWIDTH. THE PROPOSED ADCS ARE EXPECTED TO ACHIEVE 16.5 EFFECTIVE BITS AT SOMHZ BW OR 1.5 EFFECTIVE BITS AT SOGHZ BW. THESE ADCS HAVE BOTH SMALL AREA AND LOW-POWER DISSIPATION, THEREFORE MANY CHANNELS CAN BE IMPLEMENTED ON A SINGLE SUBSTRATE. MULTIPLE CHANNELS CAN BE SYNCHRONIZED BY A SINGLE IOOGHZ CLOCK. IN PHASE I, WE WILL COMPLETE THE ANALYSIS OF THIS CLASS OF ADCS AND DEMONSTRATE ITS KEY COMPONENTS OPERATING AT MULTI-GHZ CLOCK FREQUENCIES. IN PHASE II, WE WILL PRODUCE A WORKING PROTOTYPE ADC.