HIGHLY PARALLEL ARRAYED ANALOG TO DIGITAL CONVERTER (HI-PAA/D)

ISC IS DEVELOPING A NOVEL APPROACH OF ACHIEVING HIGH PERFORMANCE ANALOG-TO-DIGITAL CONVERSION THROUGH THE USE OF VERY EFFICIENT LOW-SPEED ADCS (ANALOG-T0-DIGITAL CONVERTERS) OPERATING IN PARALLEL. ON CHIP CIRCUITRY CAN ACCOMMODATE TUNABLE PREFILTERING TO BAND LIMIT THE SIGNAL TO BE DIGITIZED. PREAMPLIFICATION AND/OR DEMULTIPLEXING MAKE THE PROPOSED DEVICE IDEAL FOR LOW LEVEL MULTICHANNEL SIGNAL ACQUISITION FROM GRID ARRAY SENSORS IN THE FIELD OF BIOLOGY AND OPTICAL SENSING. THE APPROACH RELIES ON COMBINING HUNDREDS OF CHANNELS OF SINGLE SLOPE ADCS IN A SINGLE IC. NUMEROUS ICS ARE STACKED ON A 3-D CONFIGURATION WHICH FORM STACKS. THE NUMBER OF ICS PER STACK IS A VARIABLE, DEPENDENT ON THE APPLICAITON AND CONVERSION BANDWIDTH DESIRED. SIMPLE STACKS COULD CONTAIN GREATER THAN 1,000 ADC CHANNELS OPERATING IN PARALLEL. EVEN GREATER PARALLELISM CAN BE OBTAINED BY ASSEMBLING THE STACKS ON A SUBSTRATE SO THAT GREATER THAN 10,000 SINGLE SLOPE ADCS CAN BE MADE TO OPERATE IN PARALLEL IN A PACKAGE APPROXIMATELY TWO CUBIC INCHES. THE PROGRAM WILL FOCUS ON SPECIFICATION GENERATION, ARCHITECTURE DEVELOPMENT, AND PRELIMINARY PACKAGING DESIGN IN ORDER TO DETERMINE FEASIBILITY OF PRODUCING A PROTOTYPE FOR A LATER PHASE.