Micro-Architecture Development Tools for Embedded Processing

EDAptive Computing, Inc. (EDAptive) and Dr. Ranga Vemuri of the University of Cincinnati present a unique and commercially viable solution to the problem of design space exploration, tradeoff analysis, and performance evaluation of embedded, system-levelmalleable micro-architectures. Our Embedded Micro Architecture SWEPT Simulator and Integrated Design Space Exploration and Tradeoff ANalysis Tool (ASSISTANT) program will apply previous research work in performance modeling and evaluation techniquesutilizing attributed nodes-only graph grammars to the problem of parameterization, manipulation, and simulation of various design space constraints. Specifically, we propose ASSISTANT with the following capabilities: 1) aid design engineers in thedevelopment, debug, verification, and generation of parameterized, executable design models automatically configurable at run-time for various embedded, system-level micro-architectures; 2) provide an easy-to-use shell interface for hardware applicationengineers to enter parameter data, configure, simulate, and debug the executable models for design space exploration and tradeoff analysis; 3) provide a procedural interface for the invocation of the executable models from third party tools. To accomplishthis task, we will utilize Dr. Vemuri's research work in a performance description language suited for such design and modeling scenarios called PDL+.The technology developed under this SBIR applies to both military and commercial sectors and can be usedin design and development environments for application and design engineering targeting system-level embedded, heterogeneous, and malleable computing hardware.