Broadband Agile Interface Networking System

The U.S. Navy is seeking development of a high-speed interface within the MK41 Vertical Launch System architecture. To address this Navy need, Intellisense Systems, Inc. (Intellisense) proposes to develop a new Broadband Agile Interface Networking (BRAIN) system based on integration of a technology readiness level 9 system on chip, such as a Xilinx chip, with custom power, carrier, and backplane circuits and a novel rugged housing. All BRAIN circuit developments will be supported by Systems Modeling Language (SysML) digital modeling. Specifically, the innovative adaptation of existing VITA and modular open systems architecture standards and SysML modeling tools achieves a plug-and-play solution without any required user configuration once installed. In Phase I, Intellisense will develop a concept for a common high-speed interface processor to provide missile digital data that meets the parameters in the description. We will also demonstrate that the concept can feasibly meet the requirements through analysis, modeling, and experimentation of materials of interest. During the Phase I Option, Intellisense will finalize the initial design specifications and capabilities description to build a prototype solution in Phase II. The Phase I effort will include prototype plans to be developed in Phase II. In Phase II, we will further enhance the design and develop and deliver notional full-scale prototype(s) that demonstrate functionality under the required service conditions, including thermal stresses.