Low-cost Mid-wave Infrared Focal-Plane Arrays through Direct-on-Read Out Integrated Circuit Detector Fabrication

U.S. Navy platforms have a need for high resolution and low cost MWIR cooled sensor solutions for situational awareness in clustered target environments, and in some cases, Attritable use cases.  The heterogenous and wafer-scale integration of III-V MWIR detectors to Si read-out integrated circuits (ROICs) can be an attractive approach to reduce the cost of the focal plane array and enable ultra high definition arrays to be manufactured more affordably.  The cost reduction is achieved by a parallelized approach in wafer-scale fabrication, in lieu of more serialized die-to-die (D2D) approaches used conventionally. Under the associated Phase I SBIR effort, we have demonstrated a 3” SLS epi-transfer process onto 4” Silicon surrogate wafers, and realized comparable performance HOT MWIR test diodes to as-grown SLS detectors on GaSb.  While the Silicon surrogate wafers simulate the mechanical and CTE properties of Silicon ROICs, the practical objective would be to realize a III-V MWIR epi-transfer process on large diameter Silicon ROIC wafers, and fabricate focal plane arrays without degradation in performance. Attollo plans to utilize 5” SLS wafers grown on GaSb in the Base program, perform wafer integration with an Attollo ROIC, and fabricate the FPAs at the wafer-scale to demonstrate performance and yield statistics as compared to the conventional D2D fabrication approach.  If the Option phase is excercised, we will increase the detector wafer diameter to 6” InAsSb detectors grown on GaAs, which has the promise in scalability to 8” diameter wafers based on commercially available GaAs substrates.