Photonic Processing with High Speed Interconnects

By significantly accelerating convolution neural networks (CNN) beyond the limits of electronic computation, high speed photonic processing and interconnects have the potential to dramatically advance the speed and complexity of AI/ML-based systems. This program’s objective is to demonstrate a photonic processor system that uses a state-of-the art AI/ML architecture to classify targets from 4K, 480 fps camera imagery, while defining a near-term path to a photonic integrated circuit (PIC)-based ATR system that processes speed photonic processor CNN implementation • The University of Pittsburgh (Dr. Nathan Youngblood) recently demonstrated an integrated photonic hardware accelerator (tensor core) that is capable of computing general matrix-vector operations at speeds of trillions of multiply-accumulate operations per second (Tera-MAC/s). This approach to photonic computing can easily exceed the compute density of state-of-the-art digital processors by >1000×, leading to high performance computing systems with exceptional SWaP metrics. Our groundbreaking research provides a well-defined path to a future photonic integrated circuit (PIC) implementation of the discrete-component version proposed for this DP2 program. Tera-MAC/s PICs exhibit much lower energy consumption and much higher bandwidth than their electrical counterparts. They are also superior to traditional free-space optical approaches (e.g., 2f, 4f correlators) for AI/ML applications because their programmable tera-MAC/s computational ability can be applied to all layers of deep CNNs. We propose a 6-month Phase II “sub-phase” program to finalize requirements, refine the architecture, and develop a preliminary ATR system design. The system accepts PCIe imagery from a Ximea 4K 480 fps camera and formats that data for wavelength division multiplexed (WDM) fiber-optic transmission to a photonic processor that implements highly parallelized, first-layer CNN feature extraction. We will also complete a software simulation of our photonic processor to model its performance in a photonic ATR system. Also described (but not priced) in our proposal is a 12-month follow-on effort to complete the detailed HW/SW design and integrate/test the completed photonic processor-based ATR system. Following the demonstration we will deliver the integrated ATR system, documentation and final report.