SBIR/STTR Research Award

High Fidelity Analog Integration Techniques for High Temperature Applications

Award identifier 0fd1b98d6e4745da87ffacef4aebe4cd649a4aa6aa87427762e4023fd64ede50Awarding agency Department of Defense · Defense Advanced Research Projects Agency

Award amount

$1,492,065

Program and phase

SBIR · Phase II

Award year

2022

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Award details

Awarding agency
Department of Defense
Branch
Defense Advanced Research Projects Agency
Recipient company
OZARK INTEGRATED CIRCUITS INC
Proposal award date
2022-06-02
Contract end date
2024-07-01
UEI
C3JNF19C7DK8
Solicitation number
20.1
Topic code
NASA S4.04

Research abstract

The battlefield of the future and today, is based on data; and the ability to act upon this data. Data provides the foundation of everything from intelligence, situational awareness, and force readiness. Acquiring data in extreme environments requires analog and mixed signal electronics that don’t need thermal management. Integrated circuits (ICs) made with silicon carbide (SiC) semiconductor technology at research laboratories, such as NASA ‘s JFET-R, has been shown to work reliably for 100s to 1000s of hours at 500°C. The next urgent step is to migrate the SiC process from R&D availability to regular quarterly production. Migration of this technology into a commercial-scale capable fab is the next logical step.  General Electric Research Center (GERC) stands ready to work with Ozark IC to migrate the essential metalization steps (“Back End of Line”) to support greater JFET-based silicon carbide production. Analog and mixed-signal data acquisition systems also require precision passive elements, which are scarce if there is no thermal management. This second part of this project will develop additively manufactured (AM) passive structures designed to heterogeneously integrate with the ICs from the migrated JFET-R process. These AM passives will be printed and characterized over the full temperature range using passive test structures for schematic capture and simulation via thermally hardened SPICE models. This work will culminate in the design, fabrication, and packaging of an analog system for demonstration at high temperature. This system will include an analog JFET-R chip heterogeneously integrated with AM passives fabricated to match a schematic design of the complete system.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

37 SBIR/STTR records share this UEI (2012–2024). Reported award amounts total $19,866,110. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Energy, National Aeronautics and Space Administration, Department of Defense, National Science Foundation

Agency intelligence

Department of Defense

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