High Dynamic Range Real-Time LIDAR Digitizer and Processor

The US Navy needs an advanced Light Detection and Ranging (LIDAR) digitizer ASIC for remote sensing of oceans and the atmosphere for anti-submarine warfare (ASW) applications such as distant target ranging from smaller platforms on unmanned air and undersea vehicles. Current specifications of available real-time processing digitizers for profiling LIDARs are constrained by their limited range and magnitude information due to effective number of data conversion bits and bandwidth available. This is evidenced by design specifications of such analog to digital converters (ADCs) presently used in LIDAR designs. So, there is a need to improve the size, weight, power and cost (SWaP-C) of these designs to make LIDARs viable in smaller platforms as the SBIR demands. With LIDARs becoming ubiquitous on autonomous vehicles and other unmanned aerial and undersea vehicles it is important to have form factor improvements that improve their accessibility in these critical environments where no latency can be tolerated. As the Navy has stated, ōa critical consideration in balancing the design of a remote sensing LIDAR system is the types of errors the system can tolerate. Two such errors that cannot be tolerated are non-linearity in the logarithmic response and/or gain, and offset errors between channels.ö AlphacoreÆs digitizer ASIC solution being a single channel ADC without channel stacking or logarithmic amplification, providing high dynamic range and accuracy, will overcome these challenges, and be of great benefit to emerging DoD and commercial demand for this performance. To address this need in the SBIR N192-063 Phase II program, Alphacore started development in Phase I of a low-cost, Multi-spectral, Multi-channel, High-Resolution (HR), Wideband (WB) LIDAR Digitizer ASIC that comprises all the NavyÆs required ADC specifications. AlphacoreÆs pioneering calibration techniques and silicon-tested, truly innovative digitizer architectures, achieve breakthrough sensing resolutions at high sampling rates. The ASIC addresses all the above-mentioned limitations: it has 1 GS/s (gigasamples per second) sampling rate, it functions up to 50MHz input bandwidth with 17 ENOB and up to 500MHz input bandwidth with ~1-bit drop in ENOB, its size is only 1/8 cubic inch, weight is less than an ounce, and power dissipation less than 300mW. An additional benefit is that this ASIC solution does not suffer from latency. The digitizer architecture is based on a pipeline ADC topology, that uses known and novel circuit techniques to achieve high sampling rate and desired ENOB. The ADC also offers an easy to use interface to contemporary FPGAs adding to the productÆs versatility and commercialization to circuit/system designers.