Improving Threshold-Voltage-Defined Logic Families for Bulk CMOS Logic Obfuscation

This project aims to enhance hardware security through advanced logic obfuscation using threshold-voltage-defined (TVD) logic families. Traditional approaches to chip securityósuch as dummy gates, programmable cells, or logic lockingóare increasingly ineffective against reverse engineering, side-channel analysis, and Boolean satisfiability (SAT) attacks. While techniques like look-up tables and finite-state machines provide better protection, they suffer from significant area, power, and delay overheads and remain vulnerable to advanced imaging and machine learning-based attacks.To overcome these limitations, we propose improvements to E-TVD logic, which encodes logic functions using transistors with identical layouts but different threshold voltages. This technique offers strong resistance to imaging, SAT, and side-channel attacks, while maintaining robustness across process, voltage, and temperature (PVT) variations. Compared to earlier TVD implementations, E-TVD significantly reduces transistor count and power consumption without compromising security.Building on E-TVD, we will develop two advanced variantsóE-TVD+ and E-TVD++óthat offer greater efficiency and expanded resistance to emerging threats such as laser fault injection and transistor self-heating. E-TVD++ will also support limited post-fabrication reprogramming, enabling each chipís logic functions to be dynamically redefined. This feature further complicates reverse engineering and enhances resilience against both physical and electrical probing.These improvements promise to deliver compact, energy-efficient, and highly secure logic suitable for deployment in sensitive systems and advanced commercial applications.