Radiation hardened double sided Low-Gain Avalanche Diode (LGAD) with small pixel readout for 5D tracking

The current generation of Low-Gain Avalanche Diodes (LGADs) utilize “reach-through” deep implants to provide high field gain layer. These are a recent class of silicon devices developed (mainly) to detect MIPS. They are built on thin silicon substrates, order of 50 microns, and they are engineered to have an amplification in the order of a few tens. They provide fast signals at the expense of a poor spatial resolution, being impossible to pattern them finely. New generation of LGADs are therefore needed and a few have arisen at the attention of the scientific community: Cactus Materials, Inc. is developing radiation hardened AC-LGADs and Deep-Junction LGADs, having a 100% fill factor (no dead areas) and arbitrarily fine-pitch electrodes. We have conceived a new family of LGAD structures potential to provide 5D (X, Y, Z, T, theta) tracking information based on Fermilab’s previous work and Cactus Materials, Inc. engineered substrates. The concept consists of a double sided (inverted) LGADs (iLGADs) with small pixel readout. The concept utilizes: Double sided LGADs to provide a distinctive pulse shape and “time expansion” due to slower hole drift. 3D integration of electronics for fine pitch, low capacitance pixels and complex on-sensor processing (Leveraging Cactus Materials, Inc. capabilities) Substrate engineering with epitaxial and buried layers to allow separate tuning of drift and avalanche fields (developed engineering substrates by Cactus Materials, Inc. through previous SBIR funding). Interest in angle information is motivated by the current CMS track trigger stub concept and possible future FCC-hh and muon collider background reduction applications. iLGADs can be developed with fine pixels on the hole-collecting side and anode can provide timing with coarse pitch which will lower total power and complexity. Cathode can be subdivided into small pixels which can record “primary” hole collection, then holes from gain region, double peak that reflects charge deposition pattern, in turns lower power due to large signal from the gain layer. TCAD simulation confirmed current pattern can be used to measure angle and position. A thicker detector can be optimized to measure angle or charge deposit location at some sacrifice to time resolution. The fabrication leverages from the capabilities of Cactus Materials of performing wafer-bonding, which is critical to the project and leveraging AC-LGADs and 3D integration technology previously developed or in progress through SBIR funding. Researchers from Fermi Lab will conduct TCAD for device numerical simulations, and Cactus Materials Inc. clean-rooms, bringing their capability of wafer bonding and device fabrication. Device fabrication will be performed at Cactus Materials, Inc. laboratory, including the wafer-to-wafer bonding. Dr. Islam, PI of this project, has extensive experience in semiconductor fabrication while worked at Intel Corporation, EVG, Inc and Cactus Materials, Inc. and Dr. Ron Lipton from Fermi Lab will conduct TCAD simulation.