Photonic-Storage Subsystem Input/Output (P-SSIO) Interface

The diverse workload of ever-increasing cloud and high- performance computing applications brings many challenges to traditional server-centric computing system architectures with a fixed amount of compute, memory and storage nodes. Conventional electrical interconnect approach suffers from the incapability of disaggregating the storage from the compute over few meters due to the inherent losses associated with transmitting the high bandwidth electrical signals over long distances. Furthermore, power consumption grows dramatically with high I/O and peripheral bandwidth capacity required by high- performance computing systems limiting systems with electrical interconnects as currently deployed. A more power-efficient reconfigurable interconnect fabric is required to deliver the bandwidth capacity for today’s applications that use PCIe-based storage and require high I/O rates. The objective of this SBIR effort is to design, fabricate, build and test a photonic based I/O interfaces to provide high bandwidth connectivity between the server class Peripheral Component Interconnect Express (PCIe) controllers and Non-Volatile Memory Express (NVMe) storage subsystem for DOE relevant high-performance computing applications. Freedom Photonics objective has designed and fabricated the tunable laser array and to deliver these to Columbia. Year 1 laser array utilizing discrete lasers were fabricated and delivered per schedule. Development of the base chip technology for an integrated WDM source is now ongoing according to schedule. In addition, a Phase II demonstration of low-power laser epitaxial material has been completed that allows efficient operation at 70ºC (only 30% penalty to room temperature). Additional achievements include the demonstration of the first active-passive integration using our high efficiency DFB lasers, in which an InP star coupler can be integrated. Columbia University has (1) designed and fabricated silicon photonic transceiver and switch fabrics and (2) design and implement subsystem controllers to support high-bandwidth and reconfigurable connectivity in the P-SSIO subsystem. During Year I and Year II, silicon photonic microdisk based transmitters and microring based filters were fabricated. They have been shown to be feasible and can support the PCIe Gen3 bandwidth requirements. Columbia has also completed the silicon photonic switch fabrics’ and subsystem controllers’ designs enabling dynamic resource allocation in the subsystem. The testbed demonstrated deep disaggregation of memory and PCIe resources. These initial experiments demonstrate the potential to further integrate the subsystem controller components, and to mature the switch control circuitry and packaging for future system integration. In Phase IIB, we will use Field Programmable Gate Array (FPGA) based MPSoC development boards to implement the host, endpoint, switch nodes based on the Gen3 PCIe specification. As we developed in both Phase I and Phase II, the subsystem controllers, including the optical network controller and the optical switch controller, have been shown to be functional and operational. In Phase IIB, Columbia will further integrate these subsystem controller components with the Silicon Photonic (SiP) circuit switch, mature the switch control circuitry and packaging, and compose a SiP switch unit for the system integration. Freedom Photonics will focus on the development of the optical WDM source and packaging. The proposed Phase II effort relating to source development include adapting the base laser design for compatibility with low-cost packaging and manufacturing. The Photonic Memory Controller developed have wide commercial applications in data center and telecom markets.