Energy-Efficient Reconfigurable Universal Accelerator Interconnect

Recent advances in computing systems have fundamentally changed and shaped almost every aspect of today’s society. From healthcare to finances to scientific discoveries, our everyday lives will depend more and more on computing and communication infrastructures and their capability to process and deliver critical information in real time. However, as high-performance-computing systems and datacenters already consume megawatts of power, sustainable scaling of future computing systems must consider energy-efficient, parallel, and accelerated heterogeneous processing that can be commercially deployed. The proposed project pursues energy-efficient, high-performance, and universal accelerator interfaces to sustain the ever-increasing demand for scalable and ubiquitous computing processing power. Application domains like high performance computing and machine learning now process data sets of terabytes in size, requiring increasing numbers of processing and memory resources. This is at the expense of very high-power consumption due to bottlenecks in the electrical interconnections between processing units. This project aims to significantly reduce the communication energy and latency by developing novel technologies in silicon photonic reconfigurable interconnects. These reconfigurable interconnects will optimally adapt the communication bandwidth and interconnection topology as data flow patterns change for specific application workloads. The consortium achieved the following key milestones in Phase I: (a) fabrication, packaging and testing of an 8-port 16 wavelength reconfigurable all-to-all silicon photonic fabric enabling bandwidth and topology reconfiguration among interconnected nodes; (b) fabrication and testing of low-loss and low-crosstalk integrated optical multiplexers and grating structures for multi-wavelength comb sources; (c) fabrication, packaging and system integration of silicon photonic transceivers bonded with high-speed electronic drivers; (d) assembly of a prototype accelerator board for preliminary system testing with all the components fabricated above. For Phase II project, the consortium will build upon the milestones achieved in the Phase I project to deliver the following key results: (a) 32-wavelength laser with 100GHz spacing; (b) packaged 16-port 32 wavelength reconfigurable all-to-all silicon photonic fabric with electrical control plane for driving the topology and bandwidth reconfiguration between the interconnected nodes; (c) system integration and assembly of accelerator linecards using multi-wavelength electro-optic transceivers and heterogeneous processors; (d) final system demonstration of up to sixteen accelerator linecards interconnected through the fabricated 16-port reconfigurable photonic fabric. The successful completion of this project will lead to significant improvements in energy and performance of large-scale data centers and high- performance computing systems, paving the way for the wide-spread use of emerging artificial intelligence applications which heavily rely on application-specific accelerator units.