Cryo-CMOS Nanoscale Technologies and Integrated Circuits

The US Army will benefit from integrated circuits (ICs) based on nanoscale CMOS technology, with low power consumption and enhanced noise performance, specifically designed for operation at deep cryogenic temperatures, down to 4 K, for its critical Network Command, Control and Communications equipment. The main interests for these CMOS ICs are in exciting low power sensing applications for emerging high-performance quantum computing control electronics, quantum sensing, distributed quantum information to achieve practical quantum computers.  In Phase I of this STTR program, Alphacore with Arizona State University (ASU - Research Institution) will perform low-temperature (cryogenic) device characterization and modeling. We will perform measurements of device characteristics on MOSFETs of different technology nodes and structural types, such as nanoscale bulk-MOSFET, FinFET, and FD-SOI CMOS technologies, across the entire temperature range from room temperature to cryogenic temperature of 4 K. The STTR team will extract the temperature-dependence of key parameters including Ion, Ioff, SS, Vt, gm, and S-matrix; investigate low-temperature effects including dopant freeze-out, kink effect, Vt mismatch, etc. The Phase I plan includes development of physics-based device models to match characterization, and development of compact circuit models for use in circuit simulators. Phase I research will help identify one or more existing CMOS foundry processes for designing and fabricating cryo-CMOS prototype circuits in Phase II. The chosen process will be thoroughly characterized and modeled during Phase I.