Low Temperature Junction Formation for Image Sensors and Charge-Coupled Devices

Measuring the paths and positions of subatomicparticles is at the core of high energy physics (HEP) research. Such measurements require detectors of extraordinary speed and resolution, and electrical components must endure extremes of temperature, electromagneticfields, and radiation. To support the high luminosity upgrades at ATLAS and CMS, both pixel size reduction, which increases resolution, and "thinning" of the substrate, which improves high-energy radiation resistance are critical. Many detectors that are critical to HEP research would benefit from atechnology that allows low- temperature, CMOS compatible annealing of dopants and defects in semiconductors. Someexamples include: monolithic CMOS sensors forvertex and tracking systems; thin diode array sensors forhybrid detectors; entrance windows on CCDs and APSs forcosmology, and defect removal in CCDs and APSs. To ensure a productive application to the particle physics community, acost effectivealternativeto traditional radiation and laser based heat transfer is being proposed. A newlydeveloped capacitive induction annealing (CIA) system allows forselective heating of dopants in silicon. Through interfacial polarization mechanism the dopants becomepolarized in the capacitive electrical field, allowing them to become selectively activated while the bulk silicon temperature remains at lowertemperatures. The result is dopant activation with negligible dopant diffusion, high activation efficiency of dopants (B/P/As) with no damage to the CMOS devices on the front side, even with the presence of metals. CIA system should prove to be an efficient way to achieve shallow entrance windows in silicon sensors without the use of expensiveand complex process flows associated with using silicon-on-insulator(SOI) wafers. Phase 2 objectives are to demonstrate post-processed junctions, on monolithic CMOS sensors, demonstrating good diode IV and dark current characteristi cs, as well as radiation sensing, using CIA for backside junction post-process. We will be investigating new types of sensormaterials, such as germanium, SiC and diamond substrates, at different wafersizes and thicknesses to optimize activation efficiency and device performance using Capacitive Inductive Annealing (CIA). We will perform demos, for each developed sensorapplication, on our CIA chamberinstalled at DSG’s lab to optimize wafer uniformity and maximize throughput with the final objective to design, build and test a first article production system to support state-of-the art back-side CMOS image sensors (CIS) manufacturing. Partnering with global leaders in semiconductorfabrication, CIA technology has demonstrated, on vertical structures (3DNAND), a 2X improvement in mobility and on 7nm FinFETstructures, with 10:1 aspect ratio, uniform 3D densification of dielectrics. CIA technology willhelp drive furtherminimization of integrated circuits in all semiconductorsectors (imagesensors, logic, power and memory).