Post Thermal Processing by Capacitance Induced Annealing

Measuring the paths and positions of subatomic particles is at the core of high energy physics (HEP) research. Such measurements require detectors of extraordinary speed and resolution, and the electrical components must endure extremes of temperature, electromagnetic fields, and radiation. To address these challenges both pixel size reduction, which increases resolution, and "thinning" of the substrate improves high-energy radiation resistance. Many detectors that are critical to high-energy physics research would benefit from a technology that allows low -temperature, CMOS compatible annealing of dopants and defects in semiconductors. Some examples include: monolithic CMOS sensors for vertex and tracking systems; thin diode array sensors for hybrid detectors; entrance windows on CCDs and APSs for cosmology, and defect removal in CCDs and APSs. To ensure a productive application to the particle physics community, a cost effective alternative to traditional radiation based heat transfer is being proposed. A newly developed capacitive induction annealing (CIA) system allows for selective heating of dopants in silicon. The dopants become polarized in the microwave chamber, allowing them to become activated while the bulk silicon temperature remains at lower temperatures. The result is dopant activation with negligible dopant diffusion. CIA system should prove to be an efficient way to achieve shallow entrance windows in silicon sensors. The benefits of low temperature (<500C) junction formation allow for high activation efficiency of dopants (B/P/As) with no damage to the devices on the front side CMOS or CCD, even with the presence of metals (e.g. Al). Phase 1 objectives are to demonstrate post-processed junctions, with functional diode terminals, using P-I-N diode radiation sensors. This includes demonstrating good diode IV characteristics and dark current measured on the sensor wafers, as well as radiation sensing. Also to demonstrate that the post-processed junctions works with CMOS imagers by building a fully depleted CMOS imager using CIA for backside junction post-process. Partnering with global leaders in semiconductor fabrication, CIA technology has demonstrated, on vertical structures (3D NAND), a 2X improvement in mobility. This is due to a higher retained dopant dose in silicon channels “pipes” from selective heating. CIA technology will help drive further minimization of integrated circuits in all semiconductor sectors (image sensors, logic, and memory.