SBIR/STTR Research Award

20 GSPS ADC For Spectrometer Backends In Microwave Radiometers

Award identifier 5dc10e2b9b9f997111ae5b2930ec85c15fdad6eae67e6e4cfc1bd9c210c5c54bAwarding agency National Aeronautics and Space Administration

Award amount

$123,236

Program and phase

SBIR · Phase I

Award year

2020

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Award details

Awarding agency
National Aeronautics and Space Administration
Branch
Not reported
Recipient company
Alphacore, Inc.
Proposal award date
2020-08-12
Contract end date
2021-03-01
UEI
CXMPDDLFBCH3
Solicitation number
SBIR_20_P1
Topic code
S1

Research abstract

NASA Science Mission Directoratersquo;s (SMD) programs demand an innovative single-chip 6-bit 20GSPS analog to digital converter (ADC) capable of surviving and maintaining performance in extreme environments for use in next generation low-power, rad-tolerant broad band spectrometer back ends for microwave radiometers. Broadband spectrometers in Earth observing, planetary, and astrophysics missions have a critical need for greater sensitivity detector arrays for imaging, spectroscopy, and polarimetric capabilities, which can be demonstrated on ground, airborne, balloon, suborbital rocket instruments, or uninhabited aerial vehicle (UAV) platforms. Future cloud, water and precipitation missions like Soil Moisture Active Passive (SMAP) require higher frequency electronics, with small form factors and high power added efficiencies (PAE).nbsp;Alphacore proposes a competitively disruptive ADC, based on its similar solutions, to meet NASArsquo;s request for development of advance science instruments, observatories amp; sensor systems. The rad hard ADC, with Size Weight and Power (SWaP) efficiencies, will start with existingnbsp;Alphacorenbsp;validated silicon to exceed a sampling rate of 20GSPS with an effective number of bits gt;6 and a straightforward FPGA interface. The ADC consists of a high-performance, low-power design that can be developed as a stand-alone chip or licensed as an IP block for use in advanced system-on-chip (SOC) architectures. The ADC employs a silicon proven radiation hardened flash architecture using a common FD-SOI wafer process node

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

155 SBIR/STTR records share this UEI (2013–2026). Reported award amounts total $63,784,604. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Energy, Department of Commerce

Agency intelligence

National Aeronautics and Space Administration

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