SBIR/STTR Research Award

Reconfigurable Computer Architecture

Award identifier 45d325728ddc4a63131e0b8ea453c113130374477f7b56f8dd9a6ca37df4a228Awarding agency Department of Defense · Army

Award amount

$111,457

Program and phase

SBIR · Phase I

Award year

2020

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Award details

Awarding agency
Department of Defense
Branch
Army
Recipient company
CROSSFIELD TECHNOLOGY LLC
Proposal award date
2020-06-26
Contract end date
2021-03-23
UEI
EE2BD1HMA748
Solicitation number
20.1
Topic code
A20-100

Research abstract

Crossfield Technology proposes a standards-based approach to implementation of reconfigurable Field Programmable Gate Arrays (FPGAs) and System on Chip (SoC) modules that can be rapidly deployed and then upgraded as technology evolves.  FPGA technologies offer the highest degree of programmability and flexibility for functionality and interfaces of all large-scale integrated circuits. With FPGAs set to scale beyond 50 billion transistors, it seems inevitable that interconnecting the logic and memory resources in an optimum manner be a normal part of implementing an algorithm in hardware. In addition, almost any interface can be implemented in an FPGA with an appropriate physical layer device.  Similar to processors with multi-level cache memories, FPGA vendors now provide two or more types of on-die memory. Both FPGAs and processors now provide an option for in-package High Bandwidth Memory (HBM), which offers TB/s memory bandwidth for demanding applications. Unlike processors, though, the memory available to the FPGA fabric can be connected in a manner consistent with the flow of data through the algorithm. FPGAs, and some embedded processors, include multi-protocol transceivers that support common interfaces such as 1/10/40/100G Ethernet, PCI Express, DisplayPort and other serial protocols. The speed of these interfaces are on an upward trend, and are now exploiting modulation techniques such as PAM-4 to increase the Baud rate of each serial lane. It is only a matter of time before 400 Gbps and 1 Tbps links become commonplace. Crossfield is a member of SOSA and VITA, and participated in the recent Tri-Service Open Architecture Interoperability Demonstration (TSOA-ID) event held at GTRI in Atlanta, GA. At the event, Crossfield showcased two OpenVPX payload modules with high-end FPGAs that provide the programmability and many of the interfaces described in this solicitation. Two companion Solid State Memory OpenVPX modules provide 4-16 TB of non-volatile storage. All of the modules have been tested for conformance to their associated HOST Tier 3 Specifications.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

38 SBIR/STTR records share this UEI (2004–2021). Reported award amounts total $16,910,245. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense, Department of Energy, National Aeronautics and Space Administration

Agency intelligence

Department of Defense

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